A Novel Carry Skip BCD Adder Implementation Using Reversible Logic for Nanotechnology-Based Systems

Abstract

In recent years, reversible logic has emerged as a promising technology with
applications spanning low-power CMOS, quantum computing, nanotechnology, and
optical computing. Quantum computing, in particular, relies on reversible logic for its
realization. The construction of low-power and low-loss computational structures is
crucial for developing arithmetic circuits used in quantum computation, nanotechnology,
and other low-power digital circuits. This work presents optimized one-digit BCD adders
and carries skip BCD adders using new reversible logic gates. The proposed approach
aims to minimize quantum cost and optimize performance compared to existing circuits,
focusing on reducing the number of reversible gates used and minimizing garbage outputs
produced. The objective is to design faster BCD adders and provide a foundation for
building the decimal Arithmetic Logic Unit (ALU) of a Quantum CPU. The work is
implemented using Hardware Description Language (HDL), with Simulation & Synthesis
conducted on Xilinx ISE. The design targets the Xilinx Spartan 3E FPGA device. This
research contributes to the advancement of efficient and high-performance arithmetic
circuits suitable for emerging technologies such as quantum computing and
nanotechnology.